The present invention relates generally to semiconductor device fabrication and, more particularly, to circuits for protecting the gate dielectric of a field-effect transistor against electrostatic discharge (ESD) events, as well as methods for providing ESD protection and design structures for an ESD protection circuit.
Modern electronics achieve high levels of functionality in small form factors by integrating multiple functions onto a single chip. A common fabrication process that allows high levels of integration at a relatively low cost is Complementary Metal-Oxide-Semiconductor (CMOS). CMOS processes build a combination of p-type and n-type field effect transistors to implement logic gates and other types of digital and analog circuits.
Chips may be exposed to ESD events leading to potentially large and damaging currents and voltages within the integrated circuit. Increasing integration densities and performance demands on CMOS chips have resulted in reduced device dimensions. This reduction in dimensions has increased the susceptibility of integrated circuits to ESD events. Manufacturers, assemblers, and users of integrated circuits must take precautions to avoid unintentionally causing ESD events. For example, ESD prevention can be incorporated into the integrated circuit and may include special design techniques for input/output (I/O) pins and pads, as well as power supply pads. These special design techniques prevent damage to the chip both during handling after the chip is manufactured and while the chip is installed on a circuit board. Typically, this type of ESD protection operates by directing the current of an ESD event away from the internal circuits of the chip when the voltage on the protected pad exceeds a maximum allowable threshold.
One aspect of CMOS design where reduced device dimensions have increased susceptibility to ESD is the thickness of the gate dielectric of the field-effect transistors. A reduced gate dielectric layer thickness may result in a lower gate dielectric breakdown voltage, which reduces the ESD voltage that the field-effect transistor can withstand. This lower ESD voltage tolerance may reduce the ESD voltage design window between the normal operating and maximum allowable voltages on the I/O or supply pads of the chip.
Therefore, circuits that improve the breakdown resistance of the gate dielectric during ESD events, as well as methods and design structures for improving the breakdown resistance of the gate dielectric of a field-effect transistor during ESD events are needed.